Announce: vsim the VHDL-subset simulator (unmaintained)
Hi. I'd like to announce the vsim - the simulator for (small subset
of) VHDL language. Currently
the project contains pretty large Java part and is not maintained.
That's why I don't want to
publish it on Hackage. Still, as far as I now have a permission to
share the code, I would like to do it.
VSim is a VHDL simulator project aimed develop a methods of compiling VHDL code
into a high-level language (Haskell). Currently it is able to compile simple
VHDL programs, containing plain integer types, 1-dimentional arrays, records. It
supports processes, procedures, functions (partly). Breakpoints and wait
statements should work.
Simulator compile VHDL into Haskell in several steps.
Firstly, VHDL is translated into VIR-file by a translator written in Java (see
tr/ folder and runtr function in ./simenv shell script). VIR file is lisp-like
file, describing vhdl entities in a less complex manner. For example, it
contains all the port maps expanded.
Secondly, VSim tool is used to translate VIR into Haskell (see src/ folder and
runsim functino in ./simenv). VSim is a small program which translates VIR
line-by-line into Haskell program. haskell-src-exts is used to build the AST
and print it to stdout.
Finaly, Haskell program should be compiled into binary with ghc having runtime
library included (refer to src\_r/ folder and runsim function in ./simenv).
The runtime is the heart of the simulator and it's largest part.
Java part is a main headache, because it is big, unsupported and has bugs
lurking here and there. Haskell part is smaller and cleaner, but VHDL-standard
coverage is still poor. For example, signal assignments are working as if they
are declared with transport delay mechanism. Another problem is missing enum
support except of some pre-defined.